FIG. 1a shows a depiction of a bus 120. A bus 120 is a “shared medium” communication structure that is used to transport communications between electronic components 101a-10Na and 110a. Shared medium means that the components 101a-10Na and 110a that communicate with one another physically share and are connected to the same electronic wiring 120. That is, wiring 120 is a shared resource that is used by any of components 101a-10Na and 110a to communicate with any other of components 101a-10Na and 110a. For example, if component 101a wished to communicate to component 10Na, component 101a would send information along wiring 120 to component 10Na; if component 103a wished to communicate to component 110a, component 103a would send information along the same wiring 120 to component 110a, etc.
Computing systems have traditionally made use of busses. For example, with respect to certain IBM compatible PCs, bus 120 corresponds to a PCI bus where components 101a-10Na correspond to “I/O” components (e.g., LAN networking adapter cards, MODEMs, hard disk storage devices, etc.) and component 110a corresponds to an I/O Control Hub (ICH). As another example, with respect to certain multiprocessor computing systems, bus 120 corresponds to a “front side” bus where components 101a-10Na correspond to microprocessors and component 110a corresponds to a memory controller.
Owing to an artifact referred to as “capacitive loading”, busses are less and less practical as computing system speeds grow. Basically, as the capacitive loading of any wiring increases, the maximum speed at which that wiring can transport information decreases. That is, there is an inverse relationship between a wiring's capacitive loading and that same wiring's speed. Each component that is added to a wire causes that wire's capacitive loading to grow. Thus, because busses typically couple multiple components, bus wiring 120 is typically regarded as being heavily loaded with capacitance.
In the past, when computing system clock speeds were relatively slow, the capacitive loading on the computing system's busses was not a serious issue because the degraded maximum speed of the bus wiring (owing to capacitive loading) still far exceeded the computing system's internal clock speeds. The same cannot be said for at least some of today's computing systems. That is, with the continual increase in computing system clock speeds over the years, the speed of today's computing systems are reaching (and/or perhaps exceeding) the maximum speed of wires that are heavily loaded with capacitance such as bus wiring 120. Other problems associated with increasing bus speed is signal distortion.
Therefore computing systems are migrating to a “link-based” component-to-component interconnection scheme. FIG. 1b shows a comparative example vis-à-vis FIG. 1a. According to the approach of FIG. 1b, computing system components 101a-10Na and 110a are interconnected through a mesh 140 of high speed bi-directional point-to-point links 1301 through 130N. A bi-directional point-to-point link typically comprises a first unidirectional point-to-point link that transmits information in a first direction and a second unidirectional point-to-point link that transmits information is a second direction that is opposite that of the first direction. Because a unidirectional point-to-point link typically has a single endpoint, its capacitive loading is substantially less than that of a shared media bus.
Each point-to-point link can be constructed with copper or fiber optic cabling and appropriate drivers and receivers (e.g., single or differential line drivers and receivers for copper based cables; and LASER or LED E/O transmitters and O/E receivers for fiber optic cables; etc.). The mesh 140 observed in FIG. 1b is simplistic in that each component is connected by a point-to-point link to every other component. In more complicated schemes, the mesh 140 is a network having routing/switching nodes. Here, every component need not be coupled by a point-to-point link to every other component Instead, hops across a plurality of links may take place through routing/switching nodes in order to transport information from a source component to a destination component. Depending on implementation, the routing/switching function may be a stand alone function within the mesh network or may be integrated into a substantive component of the computing system (e.g., processor, memory controller, I/O unit, etc.).
FIG. 2 shows a “zoom-in” of a type of uni-directional point-to-point link that may be referred to as a “multi-lane” uni-directional point-to-point link. A multi-lane uni-directional point-to-point link includes a plurality of serial channels referred to as “lanes”. Referring to FIG. 2, as an example, component 201 may be viewed as a first component within a link-based computing system and component 202 may be viewed as a second component within a link-based computing system. The observed unidirectional point-to-point link between them 205 includes N lanes LANE1 through LANEN.
Each lane is a serial channel that can be implemented as, for example, a differential signal line, a single-ended signal line or a fiber optic channel. In operation, transmitter 203 receives data to be transmitted over the link 205 to receiver 204. Transmitter 203 spreads the data received at its input over the N lanes. For example if the input to the transmitter 203 is an 8 byte word and if N=8, then, a simple transmitter design would transmit: a first byte of the input word over lane 0; a second byte of the input word over lane 1; . . . etc.; and, the eighth byte of the input word over lane N (where N=8). The receiver 204 would receive the eight bytes, ensure their alignment, and present the 8 byte word at its output (thus completing the transfer of the word from component 201 to 202).
In other approaches, the lanes do not transport data from a same parallel word but instead are treated as separate individual communication lanes. For example, if lane 0 transmits as a first communication channel and lane 1 transmits as a second communication channel, the source of the data carried by lane 0 (e.g., that entity that sent the data to transmitter 203) would be different that the source of the data carried by lane 1.
A problem is that the transmitter is apt to be designed with circuitry (such as a CMOS circuitry) that consumes increasingly more power as the speed of the lanes increase.